A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system. FIG. 1 shows a typical computer system (10) having a microprocessor (12), memory (14), integrated circuits (16) that have various functionalities, and communication paths (18), i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system (10).
The various computations and operations performed by the computer system are facilitated through the use of signals that provide electrical pathways for data to propagate between the various components of the computer system. In a general sense, the passing of data onto a signal may be accomplished by changing, i.e., transitioning, the logical value, i.e., the logical state, of the signal. Specifically, the logical state of a signal may be transitioned by either raising the voltage of the signal or reducing the voltage of the signal. When the voltage is raised, the signal is said to be at a xe2x80x9clogic high,xe2x80x9d and when the voltage is reduced, the signal is said to be at a xe2x80x9clogic low.xe2x80x9d
An integrated circuit, such as one shown in FIG. 1, includes various types of elementary logic components that are used to store, transfer, and/or manipulate the logical values of signals. One example of an elementary logic component is a flip-flop. In general, a flip-flop is a state element, i.e., a device that stores the logical state of a signal, capable of outputting a stored signal state depending on a logical transition of a clock signal at an input of the flip-flop.
In many cases, flip-flops in integrated circuits are single edge-triggered. Single edge-triggered flip-flops store, i.e., latch, state either on a positive edge (a low to high transition) of a clock signal or on a negative edge (a high to low transition) of the clock signal. A faster data rate and some power savings can be achieved if a flip-flop is designed such that the flip-flop latches state on both the positive edge and negative edge of a clock signal. Such flip-flops are referred to as dual edge-triggered flip-flops.
FIG. 2a shows a typical dual edge-triggered flip-flop (19). As shown in FIG. 2a, the dual edge-triggered flip-flop (19) has a data input d, a data output q, and a clock signal input ck. The dual edge-triggered flip-flop (19) is designed such that a value at the data input d is transferred to the data output q on both positive and a negative edges of a clock signal clk inputted at the clock signal input ck.
FIG. 2b shows a circuit diagram of the dual edge-triggered flip-flop (19) shown in FIG. 2a. As shown, the dual edge-triggered flip-flop (19) includes a first latch (20) and a second latch (21), each formed by a pair of cross-coupled inverters. A first pass gate (22) (typically formed by a P-channel transistor coupled to an N-channel transistor) and a second pass gate (24) are coupled at terminals of the first latch (20). The first pass gate (22) and the second pass gate (24) respectively receive complemented and non-complemented versions of the clk signal. Likewise, a third pass gate (25) and a fourth pass gate (23) are coupled at terminals of the second latch (21) and respectively receive complemented and non-complemented versions of the clk signal. Accordingly, on a positive edge of the clock clk signal, the data stored by the first latch (20) is sent to data output q, and, on the negative edge of the clk signal, the data stored by the second latch (21) is sent to data output q.
According to one aspect of the invention, a dual edge-triggered flip-flop capable of being programmably reset independent of an input clock signal comprises control circuitry arranged to receive the input clock signal and a reset signal; negative edge-triggered circuitry operatively connected to the control circuitry and arranged to receive a data signal and a reset value signal, wherein the negative edge-triggered circuitry generates a first output value dependent on the control circuitry and the data signal; positive edge-triggered circuitry operatively connected to the control circuitry and arranged to receive the data signal and the reset value signal, wherein the positive edge-triggered circuitry generates a second output value dependent on the control circuitry and the data signal; and output circuitry operatively connected to the negative edge-triggered circuitry and the positive edge-triggered circuitry, wherein the output circuitry generates an output signal dependent on one selected from a group consisting of the first output value and the second output value, wherein, upon assertion of the reset signal, the output signal is set to a value of the reset value signal asynchronous of the input clock signal.
According to another aspect of the invention, a dual edge-triggered flip-flop capable of being programmably reset asynchronous of an input clock signal comprises control means for receiving the input clock signal and a reset signal; negative edge-triggered means for generating a first output value dependent on the control means and a data signal; positive edge-triggered means for generating a second output value dependent on the control means and the data signal; and output means for generating an output signal dependent on one selected from a group consisting of the first output value and the second output value, wherein, upon assertion of the reset signal, the output signal is set to a programmed value asynchronous of the input clock signal.
According to another aspect of the invention, a method for performing a dual edge-triggered flip-flop operation comprises inputting a data signal, a reset signal, and a reset value signal; latching a first value on a positive edge of an input clock signal dependent on the data signal; latching a second value on a negative edge of the input clock signal dependent on the data signal; generating an output signal dependent on the input clock signal, an enable signal, and one selected from a group consisting of the first value and the second value; and upon assertion of the reset signal, setting the output signal to a value of the reset value signal asynchronous of the input clock signal.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.